TSMC, now chugging along with its N5 process node, said it will have its evolutionary N4 node ramped up to volume production this year. The N3 node, which will provide more of a technological leap than N4, is planned to go into volume production in the second half of 2022. N3 will indeed offer customers the kind of performance improvements they might hope for from a major node jump, though the speed improvement will be at the low-end of TSMC’s projected aspirations from last year; the company also just missed its target for density improvement.
The foundry also highlighted the participation of its EDA partners in helping to support the N3 node, to assure eager chip designers that the tools to design and test ICs for N3 will be ready and available. Synopsys jumped the gun; it announced its tools for supporting N3 a full week before TSMC’s event. Cadence subsequently had its quarterly earnings call and mentioned its products supporting N3 only after being chided by an analyst for not responding immediately to Synopsys. Siemens waited until the opening day of TSMC’s conference to announce its N3 tools.
L.C. Lu, TSMC’s vice president of its design and technology platform, presented the details about the company’s updated manufacturing capabilities. N4, the “easy migration path from N5,” will start volume production this year, and provide a 6% decrease in die area. It is, as it was intended and advertised to be, a modest shrink.
Lu started by offering some historical statistics about the jump from N7 to N5, providing perspective for the coming improvements from N5 to N3 (see accompanying table, above right). The logic density improvement in the latest node jump will be less than the density improvement in the previous one — and less than hoped for. The speed improvement will also be less this time around, but at least the number was in the target range.
The benchmark for comparisons was an Arm A72 core. Lu said the numbers will certainly be different for different products, but that the results achieved with the Arm core will be a good reference for other product designs.
TSMC has been tweaking the processes at each node for specific end uses, particularly high-performance computing. HPC customers should ask for the N3 DTCO node variant. Lu said that when going from N5 to N3, customers would get a 10% speed boost at 26% less power. Going from N5 to N3 DTCO would get a 22% increase, however, but at only 16% less power. In other words, designers can get additional speed at the expense of power efficiency.
Lu also provided some architectural details on how that works. The extra 12% in speed comes from
- resizing cells (they’re taller) which reduces source resistance
- a new cell structure specifically for HPC that include faster flip-flops and a via pillar
- and a new metal design: BEOL MiM (back end of line, metal-insulator-metal).
The performance improvements that moving from N5 (or above) to N3 are not trivial. Nonetheless, the amount of improvement that each successive node affords is diminishing — there is only so much farther silicon integration can go. That is why the industry is simultaneously exploring the exact opposite path, which in English would be “disintegration” — a word which, given the connotation, the industry perhaps wisely eschewed in favor of “disaggregation.”
…Disaggregation in the form of splitting off functions that used to be separate, but then were brought on-chip, and now are best spun off again. There are some pretty big challenges splitting an SoC into multiple chips — or chiplets. Lu explained that system partitioning requires decisions on
- Packaging (the choices TSMC will make available include CoWoS, InFO_PoP, InFO_3D, and SOIC),
- Symmetrical versus asymmetrical design partitioning, and
- Balancing system performance, power, area, cost, and thermal hotspots.
The necessity of thermal analysis very early in the design is new to chiplets, Lu said. The old way of doing thermal analysis doesn’t work with chiplets, so TSMC worked with its EDA partners to figure out accurate methods.
Performance testing is also a challenge because test has always been about testing a single chip. Now the issue is how to access multiple chips and test them alone and together, especially given all the packaging and interconnect options. Lu said the IEEE 1149.1/1838 standard helps define how to access multichip architectures for test.
TSMC is also putting greater emphasis on RF. Lu reminded attendees (well, viewers — the event is virtual) that TSMC has been in high volume production at 28 nm for several years; that node is called N28. The next node will be called N16FFC. Ordinarily, there is minimal benefit to be gained by reducing the size of RF circuitry, but TSMC appears to be interested in catering to companies with mixed-signal designs. Lu pointed out that the DC power reduction of N16FFC compared to the N28 node will be 25%, which Lu said will be “best for digital-intensive millimeter wave applications.”
And, because RF expertise continues to be in short supply, TSMC is trying to make it easier for designers to crank out RF circuitry. “In cooperation with our EDA partners we offer a complete RF PDK and design flows that can help streamline RF design,” Lu said. The company has 35 individual design tools (several from each major supplier), along with reference designs.
N3 by design
At the TSMC event, Siemens announced that its products certified for TSMC’s N3 and N4 processes include the Calibre nmPlatform, Siemens’ physical verification solution for IC sign-off, as well as the Analog FastSPICE Platform, which provides circuit verification for nanometer analog, radio frequency (RF), mixed-signal, memory, and custom digital circuits. Siemens also said it has also been working closely with TSMC on advanced process certifications for Siemens’ Aprisa place-and-route solution.
Siemens has also partnered with TSMC to build a design for testability (DFT) flow for TSMC’s 3D silicon stacking architecture, based on the EDA vendor’s Tessent software.
Last week, Synopsys announced that TSMC has certified its digital and custom design platforms for TSMC’s 3nm technology. According to the vendor, improvements in the digital design flow it supports include faster timing closure, full-flow correlation from synthesis to place-and-route to timing, as well as physical signoff. The platform has been enhanced to deliver improved synthesis and global placer engines that optimize library cell selection and placement results. To support TSMC’s ultra-low-voltage design closure, the Synopsys optimization engine has been improved to use new footprint optimization algorithms. These new technologies, which result from the strategic partnership between the companies, will help provide a PPA boost for designs on TSMC’s N3 process, the company said.
Unlike Siemens and Synopsys, Cadence made no formal announcement in support of TSMC’s N3 announcement, but TSMC made it clear it was working with all three of the major EDA companies. The only statement from Cadence came during the question-and-answer session from the company’s recent earnings call.
Cadence CEO Anirudh Devgan said of TSMC, “we are working with them on a variety of things including integrity 3D-IC… one of the leading mobile customers did a 3D-IC solution with that with us and TSMC. And one of the key things there was the thermal profile and they used Celsius to do silicon validation that Celsius is accurate for 3D-IC temperature simulation. So I think 3D-IC is going big. And it requires multiple products and multiple implementation flows and we are pretty confident in our position.” (The quote is drawn from the transcript of the call compiled by The Motley Fool.)