Applied Materials is promoting a new approach for controlling chip fabrication steps as the semiconductor industry adopts different materials and multi-planar dimensions in the race to the 2-nm process node.
“We have so many steps and the integration between them. The complexity requires a new solution for metrology,” Maayan Bar-Zvi, Applied Materials’ business unit head, said in an interview. Bar-Zvi oversees the Patterning Division of Applied Materials’ Process Diagnostics and Control group.
Conventionally, chip makers have used the scribe lines separating dies on a silicon wafer as an optical proximate target for metrology and process control. But scribe lines of up to 30 microns are far out of proportion to semiconductor devices with geometries at the 5-nm node. Hence, the correlation between scribe lines and end devices has become much more complex. Critical chip dimensions are far smaller than the huge target used for optical calibration in the production process.
Enter the company’s latest eBeam metrology system, the PROVision 3E. With its e-beam resolution down to 1 nm, ProVision is “allowing us to measure the device on the wafer, not on the scribe line, reducing the approximation error budget,” Bar-Zvi said. The equipment is billed as allowing for the first time a massive sampling of data drawn from a silicon wafer to help speed the ramp to optimum yield. That would help boost bottom lines by billions of dollars, according to Bar-Zvi.
To that end, it’s important to find both random and systematic defects on a wafer during trial production. That requires scanning the entire wafer rather than discrete devices, he says.
With the introduction, Bar-Zvi highlighted three key transitions, the first of which is optical-based metrology using a scribe line. Another is the correlation between lithography to etch steps. Increased steps and overlays between layers have sharply reduced statistical correlation. Third is the move from single-layer patterning to multidimensional integrative control.
The company asserts metrology on a massive scale powered by AI is on the rise. “Massive data collection is getting you a meaningful signature that correlates to process issues,” Bar-Zvi said. The transition to 3D devices–from FinFET to gate all-around — requires many measurements used to understand device performance, he added.
ADI, or after-development inspection, a step that follows lithography, allows another opportunity to spot production defects before final etching. “When you go to etch, you sometimes see issues that you didn’t catch on the [lithography], so you still have failures,” Bar-Zvi noted. “Engineers are always comparing the litho-to-etch bias. You can see that sometimes you are missing something between the two steps.”
Hence, Applied Material is promoting its PROVision equipment for measuring a production device between the lithography and etch steps. The result is a single tool that combines what were previously separate process steps.
Moreover, Bar-Zvi added, the move to higher transistor density is not just about lithography. “It’s also about different materials, a whole series of different steps. So it’s not only about litho and extreme ultraviolet, it’s also about new materials, the differences between them and the integration between different steps.”
That means there’s a greater need for data sampling.
Chipmakers must monitor from single patterning to 3D integrative control, placing greater emphasis on the integrity between multiple layers. The placement of each step in the production process is critical, Bar-Zvi stressed.
Moreover, the analytical demands are so huge that AI must be brought into the process. “There is no way to analyze this data unless you use AI and machine learning,” Bar-Zvi added.
The chip equipment maker expects its new gear to fine-tune production of advanced 3D devices for memory, including DRAM or 3D NAND, as well as logic products, where it’sapplied to FinFET processes and perhaps gate all-around.
Applied Materials said it has shipped several of the new systems to customers.