All modern digital logic consists of combinatorial logic and sequential logic. Combinatorial logic is made up of gates while sequential logic comprises of flipflops. Different transistors are connected in a peculiar way to form a gate while different gates are connected to form a flipflop. Be it combinational logic or sequential logic, the fundamental cell of any chip is the transistor.
A modern chip consists of billions of transistors. For example, the latest MacBook M1 max processor unveiled in October 2021 consists of about 57 billion transistors. It can be deduced from the number of transistors that the M1 max processor comprises at least several million gates if not billions that are placed carefully in cell sites. These gates are interconnected meticulously in a logical way to get a functional chip.
Chip development occurs in different stages. We have a front-end phase that covers RTL design, design verification and DFT insertion, while in the back-end phase, we have floor-planning, clock tree synthesis and place and route. During the RTL design, the chip code is written and then simulated. Next, the design is synthesized and later put through various back-end processes while the RTL code is frozen.
In the chip developmental process, bugs are prone to occur, and it’s important to fix these bugs before tapeout to ensure no functionality is compromised in a chip. In a chip like M1 max, the probability of bug occurrence is even more because of the large transistor count. Bugs that are discovered after RTL freeze are fixed by performing engineering change order (ECO) either manually by modifying the netlist code or through tools such as Cadence Conformal or Synopsys Formality.
Figure1 This is how manual ECO flow looks like.
For small ECOs, manually changing netlist code is effective, but in the case of larger ECOs, using EDA tools is a much better option since the existing logical equivalence check (LEC) flow can be tweaked to automate the entire ECO process. In this article, we will go through the premask flatten Cadence Conformal ECO flow that is widely used in the semiconductor industry.
Steps involved in premask flatten ECO flow
Figure 2 explains the premask flatten ECO flow with Conformal. Before beginning the ECO flow, certain equivalency checks should be performed. LEC validates the design after modification without passing any test vector from testbench. These checks are faster than running regression simulations and are often used by engineers to perform sanity checks after any design change.
Figure 2 Premask flatten ECO flow is performed using Conformal.
RTL1 – Original design without ECO
RTL2 – Modified design with ECO
PNR1 – Post-routed netlist from RTL1 without ECO
SYN2 – Synthesis netlist from RTL2 with ECO
PNR2 – Post-routed netlist with ECO patch
More information on LEC and its flow can be found in the first article of this series titled “A primer on logical equivalence checking (LEC) using Conformal”.
After all the preliminary checks are completed, the synthesis netlist with ECO (SYN2) and original post-routed netlist (PNR1) are provided to the Conformal tool. These netlists are referred to as revised design and golden design, respectively. The Conformal tool reads different kinds of optimizations, such as boundary optimization and hierarchical clock gating performed by synthesis tool, and performs LEC between input golden and revised netlist. The LEC would report non-equivalent points. These non-equivalent points should be carefully reviewed as patch generation depends on these failed keypoints.
Figure 3 More details are shown about the premask flatten ECO procedure using Conformal.
The tool then generates a patch, and later, this patch is applied on golden design—PNR1 to get a new post-routed netlist with ECO (PNR2). Finally, patch optimization is done using the Cadence’s Genus synthesis tool using the provided library information. To verify the ECO patch and to ensure no other fault has cropped up, LEC is run between SYN2 and PNR2 and a clean result is expected with zero non-equivalent keypoints.
Utilizing LEC flow to do ECO
As mentioned previously, the existing LEC flow can be modified to accommodate ECO flow. The first step to do so while performing ECO is to compare golden and revised design to calculate the delta between them. This delta a.k.a. patch is later optimized and applied to golden netlist. Later, the golden netlist with patch and synthesis netlist with patch are again compared using LEC to validate the ECO. If the comparison is clean, then ECO is a success.
So, in a nutshell, we require three equivalence checks before ECO and two equivalence checks during ECO. In between the two equivalence checks during ECO, a patch is generated, applied, and optimized by the following commands:
- Generation: This command generates a hierarchical patch. The tool can also add/delete ECO pins based on patch and pin availability.
analyze_eco -hierarchical -ecopin_dofile ecopins.do patch.v -replace
- Applying patch to golden design: The generated patch is applied to golden design using the below command.
- Optimization: The patch is later optimized using the provided library information with Genus synthesis tool. Naming of instance, net, and registers in optimized patch can be controlled with appropriate arguments.
optimize_patch -workdir <working_directory>
After the RTL freeze, bugs can be discovered in the design and are eventually resolved by doing ECOs. Manually changing netlist code can be a time consuming and cumbersome process. Using EDA tools such as Conformal or Formality can automate the entire ECO process, making it faster and often provides better results compared to doing ECOs manually. Since Conformal ECO flow utilizes the existing LEC flow, it reduces the overall ECO effort by a significant margin in some cases.
Other article in this series
Disclaimer: The author does not have any association with Cadence Design Systems or Synopsys. Any specific product reference doesn’t constitute an endorsement or recommendation. The views or opinions expressed by the author do not reflect the views of the author’s employer, Marvell Technology Inc.
Deekshith Krishnegowda is an IC design engineer at Marvell Technology’s Santa Clara office.